#ifndef _PARTHUS_HW_JAL_DEFS_
#define _PARTHUS_HW_JAL_DEFS_

/******************************************************************************
 * MODULE:          hw_jal_defs.h
 * PROJECT:         BlueStream
 * MAINTAINER:      John Nelson, Ivan Griffin
 * CREATION NAME:   7.July.1999
 *
 * LICENSE:
 *     This source code is copyright (c) 2000-2004 Ceva Inc.
 *     All rights reserved.
 *
 * SOURCE CONTROL: $Id: hw_jal_defs.h,v 1.12 2009/08/14 09:51:30 xiezc Exp $
 *
 * COMMENTS:
 *
 *     There will be the requirement to present two definitions based on
 *     the register/memory addressing approach adopted.
 *     Currently a 32 bit approach is adopted. The associated HW module
 *     is generic of the approach, but will depend on correct constants.
 *
 * REVISION HISTORY:
 *     7 July 1999    Jalapeno Revision 1.0, 30 June 1999
 *    30 July 1999      Jalapeno Revision 2.4, 14 July 1999
 *    07 Oct  1999      Jalapeno Revision (jal006v2.2)
 *    15 Nov  1999      Restructured as a result of habanero introduction.
 *     3 Mar  2000      Added definitions to support register caching
 ******************************************************************************/

/*
 * the error directive had a hash include in it -- some customer
 * complain at this !!
 */
#ifndef JAL_BASE_ADDR
#error Must include "sys_config.h" for BASE_ADDR of Jalapeno/Habanero 
#endif

/****************************************************************
*
*  Define the addresses and bit positions for the Transmit Control
*  Registers. The Addresss assume a 32 bit address space.
*  The 16 bit address bus mappings are taken care of by the macros in
*  the HW_lbl.h.
*
*****************************x***********************************/

#define JAL_BD_ADDR_ADDR                     (0x00000000 + JAL_BASE_ADDR)
#define JAL_BD_ADDR_MASK                     0xFFFFFFFF                  
#define JAL_BD_ADDR_SHFT                     0                           

#define JAL_UAP_LAP_ADDR                     (0x00000000 + JAL_BASE_ADDR)
#define JAL_NAP_ADDR                         (0x00000004 + JAL_BASE_ADDR)

#define JAL_SYNC_ADDR                        (0x00000008 + JAL_BASE_ADDR)
#define JAL_SYNC_MASK                        0xFFFFFFFF                  
#define JAL_SYNC_SHFT                        0                           

#define JAL_SYNC2_ADDR                       (0x0000000C + JAL_BASE_ADDR)
#define JAL_SYNC2_MASK                       0xFFFFFFFF                  
#define JAL_SYNC2_SHFT                       0                           

#define JAL_INTRASLOT_OFFSET_ADDR            (0x00000010 + JAL_BASE_ADDR)
#define JAL_INTRASLOT_OFFSET_MASK            0x000007FF                  
#define JAL_INTRASLOT_OFFSET_SHFT            0                           

#define JAL_BIT_COUNT_ADDR                   (0x00000010 + JAL_BASE_ADDR)
#define JAL_BIT_COUNT_MASK                   0x003FF800                  
#define JAL_BIT_COUNT_SHFT                   11                           

#define JAL_CURRENT_BT_CLK_OFFSET_ADDR       (0x00000014 + JAL_BASE_ADDR)
#define JAL_CURRENT_BT_CLK_OFFSET_MASK       0x0FFFFFFF                  
#define JAL_CURRENT_BT_CLK_OFFSET_SHFT       0                           

#define JAL_BT_CLK_OFFSET_ADDR               (0x00000018 + JAL_BASE_ADDR)
#define JAL_BT_CLK_OFFSET_MASK               0x0FFFFFFF                  
#define JAL_BT_CLK_OFFSET_SHFT               0                           

#define JAL_NATIVE_CLK_ADDR                  (0x0000001c + JAL_BASE_ADDR)
#define JAL_NATIVE_CLK_MASK                  0x0FFFFFFF                  
#define JAL_NATIVE_CLK_SHFT                  0                           

#define JAL_AM_ADDR_ADDR                     (0x00000020 + JAL_BASE_ADDR)
#define JAL_AM_ADDR_MASK                     0x00000007                  
#define JAL_AM_ADDR_SHFT                     0                           

#define JAL_ENCRYPT_ADDR                     (0x00000020 + JAL_BASE_ADDR)
#define JAL_ENCRYPT_MASK                     0x00000018                  
#define JAL_ENCRYPT_SHFT                     3                           

#define JAL_USE_LF_ADDR                      (0x00000020 + JAL_BASE_ADDR)
#define JAL_USE_LF_MASK                      0x00000020                  
#define JAL_USE_LF_SHFT                      5                           

#define JAL_SLAVE_ADDR                       (0x00000020 + JAL_BASE_ADDR)
#define JAL_SLAVE_MASK                       0x00000040                  
#define JAL_SLAVE_SHFT                       6                           

#define JAL_PAGE_ADDR                        (0x00000020 + JAL_BASE_ADDR)
#define JAL_PAGE_MASK                        0x00000080                  
#define JAL_PAGE_SHFT                        7                           


#define JAL_CRC_INIT_ADDR                    (0x00000020 + JAL_BASE_ADDR)
#define JAL_CRC_INIT_MASK                    0xff000000                  
#define JAL_CRC_INIT_SHFT                    24                          

#define JAL_LOOP_ADDR                        (0x00000024 + JAL_BASE_ADDR)
#define JAL_LOOP_MASK                        0x00000001                  
#define JAL_LOOP_SHFT                        0                           

#define JAL_TEST_ECO_ADDR                    (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_ECO_MASK                    0x00000002                  
#define JAL_TEST_ECO_SHFT                    1                           

#define JAL_ECO_ERR_ADDR                     (0x00000024 + JAL_BASE_ADDR)
#define JAL_ECO_ERR_MASK                     0x0000003C                  
#define JAL_ECO_ERR_SHFT                     2                           

#define JAL_TEST_CRC_ADDR                    (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_CRC_MASK                    0x00000040                  
#define JAL_TEST_CRC_SHFT                    6                           

#define JAL_TEST_HEC_ADDR                    (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_HEC_MASK                    0x00000080                  
#define JAL_TEST_HEC_SHFT                    7                           

#define JAL_TEST_RADIO_ADDR                  (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_RADIO_MASK                  0x00000100                  
#define JAL_TEST_RADIO_SHFT                  8                           


#define JAL_TEST_FORCE_NO_DDW_ADDR           (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_FORCE_NO_DDW_MASK           0x00000400                  
#define JAL_TEST_FORCE_NO_DDW_SHFT           10                          

#define JAL_TEST_MSG_ADDR                    (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_MSG_MASK                    0x00000800                  
#define JAL_TEST_MSG_SHFT                    11                          

#define JAL_TEST_TX_SHIFT_ADDR               (0x00000024 + JAL_BASE_ADDR)
#define JAL_TEST_TX_SHIFT_MASK               0x00007000                  
#define JAL_TEST_TX_SHIFT_SHFT               12                          

#define JAL_USE_HAB_CTRL_ADDR                (0x00000024 + JAL_BASE_ADDR)
#define JAL_USE_HAB_CTRL_MASK                0x00008000                  
#define JAL_USE_HAB_CTRL_SHFT                15                                                                 

/*
 * Setup Full DWH register to allow fast clearance of all DWH registers
 */
#define JAL_DWH_ALL_REG_ADDR                 (0x00000024 + JAL_BASE_ADDR)                     
#define JAL_DWH_ALL_REG_MASK                 0xFFBF0000                                       
#define JAL_DWH_ALL_REG_SHFT                 16                                               

#define JAL_DWH_INIT_ADDR                    (0x00000024 + JAL_BASE_ADDR)                     
#define JAL_DWH_INIT_MASK                    0x003f0000                                       
#define JAL_DWH_INIT_SHFT                    16                                               


#define JAL_DWH_BY_BT_CLK_ADDR               (0x00000024 + JAL_BASE_ADDR)                     
#define JAL_DWH_BY_BT_CLK_MASK               0x00800000                                       
#define JAL_DWH_BY_BT_CLK_SHFT               23                                               

#define JAL_DWH2_INIT_ADDR                   (0x00000024 + JAL_BASE_ADDR)                     
#define JAL_DWH2_INIT_MASK                   0x3f000000                                       
#define JAL_DWH2_INIT_SHFT                   24                                               

#define JAL_WHITEN_ADDR                      (0x00000024 + JAL_BASE_ADDR)                     
#define JAL_WHITEN_MASK                      0x80000000                                       
#define JAL_WHITEN_SHFT                      31                                               

/*                                                                                            
 * Interrupt related                                                                          
 */                                                                                           
#define JAL_TIM_INTR_MSK_ADDR                (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_TIM_INTR_MSK_MASK                0x0000000f                                       
#define JAL_TIM_INTR_MSK_SHFT                0                                                

#define JAL_TIM0_INTR_MSK_ADDR               (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_TIM0_INTR_MSK_MASK               0x00000001                                       
#define JAL_TIM0_INTR_MSK_SHFT               0                                                

#define JAL_TIM1_INTR_MSK_ADDR               (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_TIM1_INTR_MSK_MASK               0x00000002                                       
#define JAL_TIM1_INTR_MSK_SHFT               1                                                

#define JAL_TIM2_INTR_MSK_ADDR               (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_TIM2_INTR_MSK_MASK               0x00000004                                       
#define JAL_TIM2_INTR_MSK_SHFT               2                                                

#define JAL_TIM3_INTR_MSK_ADDR               (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_TIM3_INTR_MSK_MASK               0x00000008                                       
#define JAL_TIM3_INTR_MSK_SHFT               3                                                

#define JAL_SLAVE_TIM0_INTR_MSK_ADDR         (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_SLAVE_TIM0_INTR_MSK_MASK         0x00000100                                    
#define JAL_SLAVE_TIM0_INTR_MSK_SHFT         8               

#define JAL_SLAVE_TIM2_INTR_MSK_ADDR         (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_SLAVE_TIM2_INTR_MSK_MASK         0x00000200                                    
#define JAL_SLAVE_TIM2_INTR_MSK_SHFT         9       

#define JAL_PKD_INTR_MSK_ADDR                (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_PKD_INTR_MSK_MASK                0x00000010                                       
#define JAL_PKD_INTR_MSK_SHFT                4                                                

#define JAL_AUX_TIM_INTR_MSK_ADDR            (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_AUX_TIM_INTR_MSK_MASK            0x00000020                                       
#define JAL_AUX_TIM_INTR_MSK_SHFT            5                                                

#define JAL_PKA_INTR_MSK_ADDR                (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_PKA_INTR_MSK_MASK                0x00000040                                       
#define JAL_PKA_INTR_MSK_SHFT                6                                                

#define JAL_PKD_RX_HDR_INTR_MSK_ADDR         (0x00000028 + JAL_BASE_ADDR)                     
#define JAL_PKD_RX_HDR_INTR_MSK_MASK         0x00000080                                       
#define JAL_PKD_RX_HDR_INTR_MSK_SHFT         7                                                

#if(PRH_BS_CFG_SYS_HW_INDIVIDUAL_TIM_INTR_CLR==1)

#define JAL_TIM_INTR_CLR_ADDR                (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM_INTR_CLR_MASK                0x000f0000
#define JAL_TIM_INTR_CLR_SHFT                16
                                             
#define JAL_TIM0_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM0_INTR_CLR_MASK               0x00010000
#define JAL_TIM0_INTR_CLR_SHFT               16
                                             
#define JAL_TIM1_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM1_INTR_CLR_MASK               0x00020000
#define JAL_TIM1_INTR_CLR_SHFT               17
                                             
#define JAL_TIM2_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM2_INTR_CLR_MASK               0x00040000
#define JAL_TIM2_INTR_CLR_SHFT               18
                                             
#define JAL_TIM3_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM3_INTR_CLR_MASK               0x00080000
#define JAL_TIM3_INTR_CLR_SHFT               19

#define JAL_SLAVE_TIM0_INTR_CLR_ADDR         (0x00000028 + JAL_BASE_ADDR)
#define JAL_SLAVE_TIM0_INTR_CLR_MASK         0x01000000
#define JAL_SLAVE_TIM0_INTR_CLR_SHFT         24

#define JAL_SLAVE_TIM2_INTR_CLR_ADDR         (0x00000028 + JAL_BASE_ADDR)
#define JAL_SLAVE_TIM2_INTR_CLR_MASK         0x04000000
#define JAL_SLAVE_TIM2_INTR_CLR_SHFT         26

#else   /* (PRH_BS_CFG_SYS_HW_INDIVIDUAL_TIM_INTR_CLR==1) */

#define JAL_TIM_INTR_CLR_ADDR                (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM_INTR_CLR_MASK                0x00010000
#define JAL_TIM_INTR_CLR_SHFT                16

#define JAL_TIM0_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM0_INTR_CLR_MASK               0x00010000
#define JAL_TIM0_INTR_CLR_SHFT               16

#define JAL_TIM1_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM1_INTR_CLR_MASK               0x00010000
#define JAL_TIM1_INTR_CLR_SHFT               16

#define JAL_TIM2_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM2_INTR_CLR_MASK               0x00010000
#define JAL_TIM2_INTR_CLR_SHFT               16

#define JAL_TIM3_INTR_CLR_ADDR               (0x00000028 + JAL_BASE_ADDR)
#define JAL_TIM3_INTR_CLR_MASK               0x00010000
#define JAL_TIM3_INTR_CLR_SHFT               16

#endif  /* (PRH_BS_CFG_SYS_HW_INDIVIDUAL_TIM_INTR_CLR==1) */

#define JAL_PKD_INTR_CLR_ADDR                (0x00000028 + JAL_BASE_ADDR)
#define JAL_PKD_INTR_CLR_MASK                0x00100000
#define JAL_PKD_INTR_CLR_SHFT                20

#define JAL_AUX_TIM_INTR_CLR_ADDR            (0x00000028 + JAL_BASE_ADDR)
#define JAL_AUX_TIM_INTR_CLR_MASK            0x00200000
#define JAL_AUX_TIM_INTR_CLR_SHFT            21

#define JAL_PKA_INTR_CLR_ADDR                (0x00000028 + JAL_BASE_ADDR)
#define JAL_PKA_INTR_CLR_MASK                0x00400000
#define JAL_PKA_INTR_CLR_SHFT                22

#define JAL_PKD_RX_HDR_INTR_CLR_ADDR         (0x00000028 + JAL_BASE_ADDR)
#define JAL_PKD_RX_HDR_INTR_CLR_MASK         0x00800000
#define JAL_PKD_RX_HDR_INTR_CLR_SHFT         23

#define JAL_PCM_SYNC_INTR_MSK_ADDR           (0x00000028 + JAL_BASE_ADDR)
#define JAL_PCM_SYNC_INTR_MSK_MASK           0x00001000
#define JAL_PCM_SYNC_INTR_MSK_SHFT           12

#define JAL_NO_PKT_RCVD_INTR_MSK_ADDR        (0x00000028 + JAL_BASE_ADDR)
#define JAL_NO_PKT_RCVD_INTR_MSK_MASK        0x00002000
#define JAL_NO_PKT_RCVD_INTR_MSK_SHFT        13

#define JAL_SYNC_DET_INTR_MSK_ADDR           (0x00000028 + JAL_BASE_ADDR)
#define JAL_SYNC_DET_INTR_MSK_MASK           0x00004000
#define JAL_SYNC_DET_INTR_MSK_SHFT           14

#define JAL_SPI_NOW_CONFLICT_CLR_ADDR        (0x00000028 + JAL_BASE_ADDR)
#define JAL_SPI_NOW_CONFLICT_CLR_MASK        0x02000000
#define JAL_SPI_NOW_CONFLICT_CLR_SHFT        25

#define JAL_SER0_WRITE_CLR_ADDR              (0x00000028 + JAL_BASE_ADDR)
#define JAL_SER0_WRITE_CLR_MASK              0x08000000
#define JAL_SER0_WRITE_CLR_SHFT              27

#define JAL_PCM_SYNC_INTR_CLR_ADDR           (0x00000028 + JAL_BASE_ADDR)
#define JAL_PCM_SYNC_INTR_CLR_MASK           0x10000000
#define JAL_PCM_SYNC_INTR_CLR_SHFT           28

#define JAL_NO_PKT_RCVD_INTR_CLR_ADDR        (0x00000028 + JAL_BASE_ADDR)
#define JAL_NO_PKT_RCVD_INTR_CLR_MASK        0x20000000
#define JAL_NO_PKT_RCVD_INTR_CLR_SHFT        29 

#define JAL_SYNC_DET_INTR_CLR_ADDR           (0x00000028 + JAL_BASE_ADDR)
#define JAL_SYNC_DET_INTR_CLR_MASK           0x40000000
#define JAL_SYNC_DET_INTR_CLR_SHFT           30 
                                   
#define JAL_PG_TIMEOUT_INTR_CLR_ADDR         (0x00000028 + JAL_BASE_ADDR)
#define JAL_PG_TIMEOUT_INTR_CLR_SHFT         0x20000000
#define JAL_PG_TIMEOUT_INTR_CLR_MASK         29

/****************************************************************
*  Define the bit positions for the Common Status Registers
****************************************************************/

#define JAL_TIM_INTR_ADDR                    (0x0000002c + JAL_BASE_ADDR)
#define JAL_TIM_INTR_MASK                    0x0000000f
#define JAL_TIM_INTR_SHFT                    0

#define JAL_TIM0_INTR_ADDR                   (0x0000002c + JAL_BASE_ADDR)
#define JAL_TIM0_INTR_MASK                   0x00000001
#define JAL_TIM0_INTR_SHFT                   0

#define JAL_TIM1_INTR_ADDR                   (0x0000002c + JAL_BASE_ADDR)
#define JAL_TIM1_INTR_MASK                   0x00000002
#define JAL_TIM1_INTR_SHFT                   1

#define JAL_TIM2_INTR_ADDR                   (0x0000002c + JAL_BASE_ADDR)
#define JAL_TIM2_INTR_MASK                   0x00000004
#define JAL_TIM2_INTR_SHFT                   2

#define JAL_TIM3_INTR_ADDR                   (0x0000002c + JAL_BASE_ADDR)
#define JAL_TIM3_INTR_MASK                   0x00000008
#define JAL_TIM3_INTR_SHFT                   3

#define JAL_PKD_INTR_ADDR                    (0x0000002c + JAL_BASE_ADDR)
#define JAL_PKD_INTR_MASK                    0x00000010
#define JAL_PKD_INTR_SHFT                    4

#define JAL_AUX_TIM_INTR_ADDR                (0x0000002c + JAL_BASE_ADDR)
#define JAL_AUX_TIM_INTR_MASK                0x00000020
#define JAL_AUX_TIM_INTR_SHFT                5
                                             
#define JAL_PKA_INTR_ADDR                    (0x0000002c + JAL_BASE_ADDR)
#define JAL_PKA_INTR_MASK                    0x00000040
#define JAL_PKA_INTR_SHFT                    6
                                             
#define JAL_PKD_RX_HDR_INTR_ADDR             (0x0000002c + JAL_BASE_ADDR)
#define JAL_PKD_RX_HDR_INTR_MASK             0x00000080
#define JAL_PKD_RX_HDR_INTR_SHFT             7

#define JAL_SPI_NOW_CONFLICT_ADDR            (0x0000002c + JAL_BASE_ADDR)
#define JAL_SPI_NOW_CONFLICT_MASK            0x00000200
#define JAL_SPI_NOW_CONFLICT_SHFT            9

#define JAL_PCM_SYNC_INTR_ADDR               (0x0000002c + JAL_BASE_ADDR)
#define JAL_PCM_SYNC_INTR_MASK               0x00001000
#define JAL_PCM_SYNC_INTR_SHFT               12


#define JAL_PG_TIMEOUT_INTR_ADDR             (0x0000002c + JAL_BASE_ADDR)
#define JAL_PG_TIMEOUT_INTR_MASK             0x00002000
#define JAL_PG_TIMEOUT_INTR_SHFT             13
                                             
#define JAL_NO_PKT_RCVD_INTR_ADDR            (0x0000002C + JAL_BASE_ADDR)
#define JAL_NO_PKT_RCVD_INTR_MASK            0x00002000
#define JAL_NO_PKT_RCVD_INTR_SHFT            13
                                             
#define JAL_SYNC_DET_INTR_ADDR               (0x0000002C + JAL_BASE_ADDR)
#define JAL_SYNC_DET_INTR_MASK               0x00004000
#define JAL_SYNC_DET_INTR_SHFT               14

#define JAL_SLEEP_STATUS_ADDR                (0x0000002C + JAL_BASE_ADDR)
#define JAL_SLEEP_STATUS_MASK                0x00008000
#define JAL_SLEEP_STATUS_SHFT                15
                                             

#define JAL_SLEEP_ADDR                       (0x0000002c + JAL_BASE_ADDR)
#define JAL_SLEEP_MASK                       0x00008000
#define JAL_SLEEP_SHFT                       15

#define JAL_SLAVE_TIM0_INTR_ADDR             (0x0000002c + JAL_BASE_ADDR)
#define JAL_SLAVE_TIM0_INTR_MASK             0x00010000
#define JAL_SLAVE_TIM0_INTR_SHFT             16

#define JAL_SLAVE_TIM2_INTR_ADDR             (0x0000002c + JAL_BASE_ADDR)
#define JAL_SLAVE_TIM2_INTR_MASK             0x00020000
#define JAL_SLAVE_TIM2_INTR_SHFT             17

/*************************************
 * TX Control Registers
 ************************************/

#define JAL_TX_LEN_ADDR                      (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_LEN_MASK                      0x000003ff
#define JAL_TX_LEN_SHFT                      0
                                             
#define JAL_TX_TYPE_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_TYPE_MASK                     0x00003c00
#define JAL_TX_TYPE_SHFT                     10
                                             
#define JAL_TX_ARQN_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_ARQN_MASK                     0x00004000
#define JAL_TX_ARQN_SHFT                     14
                                             
#define JAL_TX_SEQN_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_SEQN_MASK                     0x00008000
#define JAL_TX_SEQN_SHFT                     15
                                             
                                             
#define JAL_TX_MODE_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_MODE_MASK                     0x00060000
#define JAL_TX_MODE_SHFT                     17
                                             
                                             
#define JAL_TX_L_CH_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_L_CH_MASK                     0x00180000
#define JAL_TX_L_CH_SHFT                     19
                                             
#define JAL_TX_P_FLOW_ADDR                   (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_P_FLOW_MASK                   0x00200000
#define JAL_TX_P_FLOW_SHFT                   21
                                             
#define JAL_TX_FLOW_ADDR                     (0x00000030 + JAL_BASE_ADDR)
#define JAL_TX_FLOW_MASK                     0x00800000
#define JAL_TX_FLOW_SHFT                     23


/*************************************
 * eSCO Control Registers
 ************************************/
#define JAL_ESCO_TX_LEN_ADDR                 (0x00000034 + JAL_BASE_ADDR)
#define JAL_ESCO_TX_LEN_MASK                 0x000003ff
#define JAL_ESCO_TX_LEN_SHFT                 0
                                             
#define JAL_ESCO_RX_LEN_ADDR                 (0x00000034 + JAL_BASE_ADDR)
#define JAL_ESCO_RX_LEN_MASK                 0x000ffc00
#define JAL_ESCO_RX_LEN_SHFT                 10
                                             
#define JAL_ESCO_LT_ADDR_ADDR                (0x00000034 + JAL_BASE_ADDR)
#define JAL_ESCO_LT_ADDR_MASK                0x00700000
#define JAL_ESCO_LT_ADDR_SHFT                20
                                             
#define JAL_SCO_ROUTE_ADDR                   (0x00000034 + JAL_BASE_ADDR)
#define JAL_SCO_ROUTE_MASK                   0x00800000
#define JAL_SCO_ROUTE_SHFT                   23
                                             
#define JAL_PCM_SLOT_NUM_ADDR                (0x00000034 + JAL_BASE_ADDR)
#define JAL_PCM_SLOT_NUM_MASK                0x03000000
#define JAL_PCM_SLOT_NUM_SHFT                24

#define JAL_DIN_X2_ADDR                      (0x00000034 + JAL_BASE_ADDR)
#define JAL_DIN_X2_MASK                      0x04000000
#define JAL_DIN_X2_SHFT                      26

#define JAL_DOUT_X2_ADDR                     (0x00000034 + JAL_BASE_ADDR)
#define JAL_DOUT_X2_MASK                     0x08000000
#define JAL_DOUT_X2_SHFT                     27
                                             
#define JAL_SFE_EN_ADDR                      (0x00000034 + JAL_BASE_ADDR)
#define JAL_SFE_EN_MASK                      0x10000000
#define JAL_SFE_EN_SHFT                      28

#define JAL_ESCO_PCM_ADDR                    (0x00000034 + JAL_BASE_ADDR)
#define JAL_ESCO_PCM_MASK                    0x40000000
#define JAL_ESCO_PCM_SHFT                    30
                                             
#define JAL_EDR_MODE_ADDR                    (0x00000034 + JAL_BASE_ADDR)
#define JAL_EDR_MODE_MASK                    0x80000000
#define JAL_EDR_MODE_SHFT                    31
                                             
#define JAL_PCM_FIFO_RD_ADDR                 (0x00000038 + JAL_BASE_ADDR)
#define JAL_PCM_FIFO_RD_MASK                 0x0000FFFF
#define JAL_PCM_FIFO_RD_SHFT                 0

#define JAL_PCM_SLOT_SEL_ADDR                (0x00000038 + JAL_BASE_ADDR)
#define JAL_PCM_SLOT_SEL_MASK                0xFFFF0000
#define JAL_PCM_SLOT_SEL_SHFT                16
                                             
#define JAL_PCM_FIFO_WD_ADDR                 (0x0000003C + JAL_BASE_ADDR)
#define JAL_PCM_FIFO_WD_MASK                 0x0000FFFF
#define JAL_PCM_FIFO_WD_SHFT                 0

/****************************************************************
*
*  Define the bit positions for the Transmit Status Registers
*
****************************************************************/
#define JAL_TX0_OVER_ADDR                    (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX0_OVER_MASK                    0x00000001
#define JAL_TX0_OVER_SHFT                    0
                                             
#define JAL_TX0_UNDER_ADDR                   (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX0_UNDER_MASK                   0x00000002
#define JAL_TX0_UNDER_SHFT                   1
                                             
#define JAL_TX1_OVER_ADDR                    (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX1_OVER_MASK                    0x00000004
#define JAL_TX1_OVER_SHFT                    2
                                             
                                             
#define JAL_TX1_UNDER_ADDR                   (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX1_UNDER_MASK                   0x00000008
#define JAL_TX1_UNDER_SHFT                   3
                                             
#define JAL_TX2_OVER_ADDR                    (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX2_OVER_MASK                    0x00000010
#define JAL_TX2_OVER_SHFT                    4
                                             
#define JAL_TX2_UNDER_ADDR                   (0x00000040 + JAL_BASE_ADDR)
#define JAL_TX2_UNDER_MASK                   0x00000020
#define JAL_TX2_UNDER_SHFT                   5

#define JAL_SCO_CFG_ADDR                     (0x00000044 + JAL_BASE_ADDR)
#define JAL_SCO_CFG_MASK                     0x00000FFF
#define JAL_SCO_CFG_SHFT                     0
                                           
#define JAL_SCO_CFG0_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_SCO_CFG0_MASK                    0x0000000F
#define JAL_SCO_CFG0_SHFT                    0
                                             
#define JAL_SCO_CFG1_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_SCO_CFG1_MASK                    0x000000F0
#define JAL_SCO_CFG1_SHFT                    4
                                             
#define JAL_SCO_CFG2_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_SCO_CFG2_MASK                    0x00000F00
#define JAL_SCO_CFG2_SHFT                    8
                                           
#define JAL_SCO_FIFO_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_SCO_FIFO_MASK                    0x00003000
#define JAL_SCO_FIFO_SHFT                    12

#define JAL_VCI_CLK_SEL_ADDR                 (0x00000044 + JAL_BASE_ADDR)
#define JAL_VCI_CLK_SEL_MASK                 0x0000C000
#define JAL_VCI_CLK_SEL_SHFT                 14

#define JAL_VCI_CLK_SEL_MAP_ADDR             (0x00000044 + JAL_BASE_ADDR)
#define JAL_VCI_CLK_SEL_MAP_MASK             0x00010000
#define JAL_VCI_CLK_SEL_MAP_SHFT             16

/* 
 * RGB 22/08/01 - new bit added for switching between codec types 
 */
#define JAL_CODEC_TYPE_ADDR                  (0x00000044 + JAL_BASE_ADDR)
#define JAL_CODEC_TYPE_MASK                  0x00020000
#define JAL_CODEC_TYPE_SHFT                  17

#define JAL_VCI_SYNC_DIR_ADDR                (0x00000044 + JAL_BASE_ADDR)
#define JAL_VCI_SYNC_DIR_MASK                0x00040000
#define JAL_VCI_SYNC_DIR_SHFT                18

#define JAL_SYNC_LS_ADDR                     (0x00000044 + JAL_BASE_ADDR)
#define JAL_SYNC_LS_MASK                     0x00080000
#define JAL_SYNC_LS_SHFT                     19

#define JAL_MSB_INPUT_ADDR                   (0x00000044 + JAL_BASE_ADDR)
#define JAL_MSB_INPUT_MASK                   0x00100000
#define JAL_MSB_INPUT_SHFT                   20

#define JAL_SIGN_INPUT_ADDR                  (0x00000044 + JAL_BASE_ADDR)
#define JAL_SIGN_INPUT_MASK                  0x00200000
#define JAL_SIGN_INPUT_SHFT                  21

#define JAL_1S_INPUT_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_1S_INPUT_MASK                    0x00400000
#define JAL_1S_INPUT_SHFT                    22
                                             
#define JAL_2S_INPUT_ADDR                    (0x00000044 + JAL_BASE_ADDR)
#define JAL_2S_INPUT_MASK                    0x00800000
#define JAL_2S_INPUT_SHFT                    23

#define JAL_SIGN_EXTENSION_INPUT_ADDR        (0x00000044 + JAL_BASE_ADDR)
#define JAL_SIGN_EXTENSION_INPUT_MASK        0x01000000
#define JAL_SIGN_EXTENSION_INPUT_SHFT        24
                                             
#define JAL_SIGN_EXTENSION_OUTPUT_ADDR       (0x00000044 + JAL_BASE_ADDR)
#define JAL_SIGN_EXTENSION_OUTPUT_MASK       0x02000000
#define JAL_SIGN_EXTENSION_OUTPUT_SHFT       25

#define JAL_MSB_OUTPUT_ADDR                  (0x00000044 + JAL_BASE_ADDR)
#define JAL_MSB_OUTPUT_MASK                  0x10000000
#define JAL_MSB_OUTPUT_SHFT                  28
                                             
#define JAL_SIGN_OUTPUT_ADDR                 (0x00000044 + JAL_BASE_ADDR)
#define JAL_SIGN_OUTPUT_MASK                 0x20000000
#define JAL_SIGN_OUTPUT_SHFT                 29
                                             
#define JAL_1S_OUTPUT_ADDR                   (0x00000044 + JAL_BASE_ADDR)
#define JAL_1S_OUTPUT_MASK                   0x40000000
#define JAL_1S_OUTPUT_SHFT                   30
                                             
#define JAL_2S_OUTPUT_ADDR                   (0x00000044 + JAL_BASE_ADDR)
#define JAL_2S_OUTPUT_MASK                   0x80000000
#define JAL_2S_OUTPUT_SHFT                   31


/****************************************************************
*
*  Define the bit positions for the Receive Control Rgeisters
*
****************************************************************/

#define JAL_RX_MODE_ADDR                     (0x00000048 + JAL_BASE_ADDR)   /* Combination of RX_EN and FULL_WIN */
#define JAL_RX_MODE_MASK                     0x00000003
#define JAL_RX_MODE_SHFT                     0

#define JAL_SYNC_ERR_ADDR                    (0x00000048 + JAL_BASE_ADDR)
#define JAL_SYNC_ERR_MASK                    0x000007C0
#define JAL_SYNC_ERR_SHFT                    2

#define JAL_ABORT_ON_FEC_FAIL_ADDR           (0x00000048 + JAL_BASE_ADDR)
#define JAL_ABORT_ON_FEC_FAIL_MASK           0x00000080
#define JAL_ABORT_ON_FEC_FAIL_SHFT           7

#define JAL_ERR_SEL_ADDR                     (0x00000048 + JAL_BASE_ADDR)
#define JAL_ERR_SEL_MASK                     0x00000e00
#define JAL_ERR_SEL_SHFT                     9
                                             
#define JAL_WIN_EXT_ADDR                     (0x00000048 + JAL_BASE_ADDR)
#define JAL_WIN_EXT_MASK                     0x003ff000
#define JAL_WIN_EXT_SHFT                     12

#define JAL_FREEZE_BIT_CNT_ADDR              (0x00000048 + JAL_BASE_ADDR)
#define JAL_FREEZE_BIT_CNT_MASK              0x00400000
#define JAL_FREEZE_BIT_CNT_SHFT              22

#define JAL_ABORT_ON_WRONG_AM_ADDR_ADDR      (0x00000048 + JAL_BASE_ADDR)
#define JAL_ABORT_ON_WRONG_AM_ADDR_MASK      0x00800000
#define JAL_ABORT_ON_WRONG_AM_ADDR_SHFT      23

#define JAL_SYNC_EDR_ERR_ADDR                (0x00000048 + JAL_BASE_ADDR)
#define JAL_SYNC_EDR_ERR_MASK                0x0F000000
#define JAL_SYNC_EDR_ERR_SHFT                24
/****************************************************************
*
*  Define the bit positions for the Receive Status Rgeisters
*
****************************************************************/
#define JAL_RX_LEN_ADDR                      (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_LEN_MASK                      0x000003ff
#define JAL_RX_LEN_SHFT                      0
                                             
#define JAL_RX_TYPE_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_TYPE_MASK                     0x00003c00
#define JAL_RX_TYPE_SHFT                     10
                                             
#define JAL_RX_ARQN_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_ARQN_MASK                     0x00004000
#define JAL_RX_ARQN_SHFT                     14
                                             
#define JAL_RX_SEQN_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_SEQN_MASK                     0x00008000
#define JAL_RX_SEQN_SHFT                     15
                                             
#define JAL_RX_AM_ADDR_ADDR                  (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_AM_ADDR_MASK                  0x00070000
#define JAL_RX_AM_ADDR_SHFT                  16
                                             
#define JAL_RX_L_CH_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_L_CH_MASK                     0x00180000
#define JAL_RX_L_CH_SHFT                     19
                                             
#define JAL_RX_P_FLOW_ADDR                   (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_P_FLOW_MASK                   0x00200000
#define JAL_RX_P_FLOW_SHFT                   21
                                             
#define JAL_RX_FLOW_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_FLOW_MASK                     0x00800000
#define JAL_RX_FLOW_SHFT                     23
                                             
#define JAL_RX_PKT_ADDR                      (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_PKT_MASK                      0x01000000
#define JAL_RX_PKT_SHFT                      24
                                             
#define JAL_HEC_ERR_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_HEC_ERR_MASK                     0x02000000
#define JAL_HEC_ERR_SHFT                     25
                                             
#define JAL_CRC_ERR_ADDR                     (0x00000050 + JAL_BASE_ADDR)
#define JAL_CRC_ERR_MASK                     0x04000000
#define JAL_CRC_ERR_SHFT                     26
                                             
#define JAL_RX_HDR_ADDR                      (0x00000050 + JAL_BASE_ADDR)
#define JAL_RX_HDR_MASK                      0x08000000
#define JAL_RX_HDR_SHFT                      27

#define JAL_FEC_ABORT_ADDR                   (0x00000050 + JAL_BASE_ADDR)
#define JAL_FEC_ABORT_MASK                   0x10000000
#define JAL_FEC_ABORT_SHFT                   28

#define JAL_AM_ADDR_ABORT_ADDR               (0x00000050 + JAL_BASE_ADDR)
#define JAL_AM_ADDR_ABORT_MASK               0x20000000
#define JAL_AM_ADDR_ABORT_SHFT               29

#define JAL_RX0_OVER_ADDR                    (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX0_OVER_MASK                    0x00000001
#define JAL_RX0_OVER_SHFT                    0
                                             
#define JAL_RX0_UNDER_ADDR                   (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX0_UNDER_MASK                   0x00000002
#define JAL_RX0_UNDER_SHFT                   1
                                             
#define JAL_RX1_OVER_ADDR                    (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX1_OVER_MASK                    0x00000004
#define JAL_RX1_OVER_SHFT                    2
                                             
#define JAL_RX1_UNDER_ADDR                   (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX1_UNDER_MASK                   0x00000008
#define JAL_RX1_UNDER_SHFT                   3
                                             
#define JAL_RX2_OVER_ADDR                    (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX2_OVER_MASK                    0x00000010
#define JAL_RX2_OVER_SHFT                    4
                                             
#define JAL_RX2_UNDER_ADDR                   (0x00000054 + JAL_BASE_ADDR)
#define JAL_RX2_UNDER_MASK                   0x00000020
#define JAL_RX2_UNDER_SHFT                   5

#define JAL_PKD_POS_ERR_ADDR                 (0x00000058 + JAL_BASE_ADDR)
#define JAL_PKD_POS_ERR_MASK                 0x0000007F
#define JAL_PKD_POS_ERR_SHFT                 0

#define JAL_ERR_CNT_ADDR                     (0x0000005C + JAL_BASE_ADDR)
#define JAL_ERR_CNT_MASK                     0x0000FFFF
#define JAL_ERR_CNT_SHFT                     0

/****************************************************************
*
*  Define the bit positions for the Serial Interface Registers
*
****************************************************************/
#define JAL_SER_CFG_ADDR                     (0x00000060 + JAL_BASE_ADDR)
#define JAL_SER_CFG_MASK                     0x7FFFFFFF
#define JAL_SER_CFG_SHFT                     0
                                             
#define JAL_SER_BUSY_ADDR                    (0x00000060 + JAL_BASE_ADDR)
#define JAL_SER_BUSY_MASK                    0x80000000
#define JAL_SER_BUSY_SHFT                    31
                                             
#define JAL_SER_TIME_ADDR                    (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_TIME_MASK                    0x000000FF
#define JAL_SER_TIME_SHFT                    0
                                             
#define JAL_SER_COMBINE_ADDR                 (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_COMBINE_MASK                 0x00000700
#define JAL_SER_COMBINE_SHFT                 8
                                             
#define JAL_SER_MASK_ADDR                    (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_MASK_MASK                    0x000F0000
#define JAL_SER_MASK_SHFT                    16
                                             
#define JAL_SER_NOW_ADDR                     (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_NOW_MASK                     0x00100000
#define JAL_SER_NOW_SHFT                     20
                                             
#define JAL_SER_SEQ_ADDR                     (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_SEQ_MASK                     0x00200000
#define JAL_SER_SEQ_SHFT                     21
                                             
#define JAL_SER_DOUBLE_ADDR                  (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_DOUBLE_MASK                  0x00400000
#define JAL_SER_DOUBLE_SHFT                  22
                                             
#define JAL_SER_MAP_SEL_ADDR                 (0x00000064 + JAL_BASE_ADDR)
#define JAL_SER_MAP_SEL_MASK                 0x00800000
#define JAL_SER_MAP_SEL_SHFT                 23
                                             
#define JAL_SER_TIM_0_ADDR                   (0x00000068 + JAL_BASE_ADDR)
#define JAL_SER_TIM_0_MASK                   0x0000000F
#define JAL_SER_TIM_0_SHFT                   0
                                             
#define JAL_SER_TIM_1_ADDR                   (0x00000068 + JAL_BASE_ADDR)
#define JAL_SER_TIM_1_MASK                   0x000000F0
#define JAL_SER_TIM_1_SHFT                   4
                                             
#define JAL_SER_TIM_2_ADDR                   (0x00000068 + JAL_BASE_ADDR)
#define JAL_SER_TIM_2_MASK                   0x00000F00
#define JAL_SER_TIM_2_SHFT                   8
                                             
#define JAL_SER_TIM_3_ADDR                   (0x00000068 + JAL_BASE_ADDR)
#define JAL_SER_TIM_3_MASK                   0x0000F000
#define JAL_SER_TIM_3_SHFT                   12
                                             
#define JAL_SER_READ_DATA_ADDR               (0x0000006c + JAL_BASE_ADDR)
#define JAL_SER_READ_DATA_MASK               0xFFFFFFFF
#define JAL_SER_READ_DATA_SHFT               0
                                             
#define JAL_SER_DATA0_ADDR                   (0x00000070 + JAL_BASE_ADDR)
#define JAL_SER_DATA0_MASK                   0xFFFFFFFF
#define JAL_SER_DATA0_SHFT                   0
                                             
#define JAL_SER_DATA1_ADDR                   (0x00000074 + JAL_BASE_ADDR)
#define JAL_SER_DATA1_MASK                   0xFFFFFFFF
#define JAL_SER_DATA1_SHFT                   0
                                             
#define JAL_SER_DATA2_ADDR                   (0x00000078 + JAL_BASE_ADDR)
#define JAL_SER_DATA2_MASK                   0xFFFFFFFF
#define JAL_SER_DATA2_SHFT                   0
                                             
#define JAL_SER_DATA3_ADDR                   (0x0000007C + JAL_BASE_ADDR)
#define JAL_SER_DATA3_MASK                   0xFFFFFFFF
#define JAL_SER_DATA3_SHFT                   0
                                             
#define JAL_STB_CFG_ADDR                     (0x00000080 + JAL_BASE_ADDR)
#define JAL_STB_CFG_MASK                     0x03FFFFFF
#define JAL_STB_CFG_SHFT                     0

#define JAL_STB_BUSY_ADDR                    (0x00000080 + JAL_BASE_ADDR)
#define JAL_STB_BUSY_MASK                    0x80000000
#define JAL_STB_BUSY_SHFT                    31

#define JAL_STB_DATA_ADDR                    (0x00000084 + JAL_BASE_ADDR)
#define JAL_STB_DATA_MASK                    0xFFFFFFFF
#define JAL_STB_DATA_SHFT                    0

#define JAL_CLK_GATE_ADDR                    (0x00000098 + JAL_BASE_ADDR)
#define JAL_CLK_GATE_MASK                    0x0000003F
#define JAL_CLK_GATE_SHFT                    0


/*******************************************************************
 *
 *     Define the bit positions for the auxilliary timer
 *     registers
 *
 *******************************************************************/
#define JAL_AUX_TIMER_ADDR                   (0x000000A0 + JAL_BASE_ADDR)
#define JAL_AUX_TIMER_MASK                   0x00003FFF
#define JAL_AUX_TIMER_SHFT                   0

/*******************************************************************
 *
 *     Define the bit positions for the piconet clock
 *     registers
 *
 *******************************************************************/
#define JAL_PICONET_INDEX_ADDR               (0x000000A4 + JAL_BASE_ADDR)
#define JAL_PICONET_INDEX_MASK               0x00000003
#define JAL_PICONET_INDEX_SHFT               0

#define JAL_SWITCH_PICONET_CLK_ADDR          (0x000000A4 + JAL_BASE_ADDR)
#define JAL_SWITCH_PICONET_CLK_MASK          0x00000004
#define JAL_SWITCH_PICONET_CLK_SHFT          2

#define JAL_UPDATE_PICONET_CLK_ADDR          (0x000000A4 + JAL_BASE_ADDR)
#define JAL_UPDATE_PICONET_CLK_MASK          0x00000008
#define JAL_UPDATE_PICONET_CLK_SHFT          3

#define JAL_PICONET_CLK_ADDR                 (0x000000A8 + JAL_BASE_ADDR)
#define JAL_PICONET_CLK_MASK                 0x0FFFFFFF
#define JAL_PICONET_CLK_SHFT                 0

/*******************************************************************
*
*      Define the bit positions for the rx_delay and tx_delay
*      control registers
*
*******************************************************************/
#define JAL_RX_DELAY_ADDR                    (0x000000B0 + JAL_BASE_ADDR)
#define JAL_RX_DELAY_MASK                    0x0000007F
#define JAL_RX_DELAY_SHFT                    0
                                             
#define JAL_TX_DELAY_ADDR                    (0x000000B0 + JAL_BASE_ADDR)
#define JAL_TX_DELAY_MASK                    0x00000F00
#define JAL_TX_DELAY_SHFT                    8

/*******************************************************************
*
*      Define the bit positions for the enc_key_len and enc_key
*      (16 bytes at C0-CF) control registers
*
*******************************************************************/
#define JAL_ENC_KEY_LEN_ADDR                 (0x000000B8 + JAL_BASE_ADDR)
#define JAL_ENC_KEY_LEN_MASK                 0x0000000F
#define JAL_ENC_KEY_LEN_SHFT                 0
                                             
#define JAL_ENC_KEY_ADDR                     (0x000000C0 + JAL_BASE_ADDR)

/*******************************************************************
 *
 *   Define the bit positions for the hop selection engine
 *
 *******************************************************************/
#define JAL_SYS_ADDR                         (0x000000D0 + JAL_BASE_ADDR)
#define JAL_SYS_MASK                         0x00000001
#define JAL_SYS_SHFT                         0
                                             
#define JAL_H_PAGE_ADDR                      (0x000000D0 + JAL_BASE_ADDR)
#define JAL_H_PAGE_MASK                      0x00000002
#define JAL_H_PAGE_SHFT                      1
                                             
#define JAL_H_SLAVE_ADDR                     (0x000000D0 + JAL_BASE_ADDR)
#define JAL_H_SLAVE_MASK                     0x00000004
#define JAL_H_SLAVE_SHFT                     2
                                             
#define JAL_PAGE_OFFSET_ADDR                 (0x000000D0  + JAL_BASE_ADDR)
#define JAL_PAGE_OFFSET_MASK                 0x00000008
#define JAL_PAGE_OFFSET_SHFT                 3
                                             
#define JAL_INDEX_MAP_ADDR                   (0x000000D0  + JAL_BASE_ADDR)
#define JAL_INDEX_MAP_MASK                   0x00000010
#define JAL_INDEX_MAP_SHFT                   4
                                             
#define JAL_CLK_DELTA_ADDR                   (0x000000D0  + JAL_BASE_ADDR)
#define JAL_CLK_DELTA_MASK                   0x000000E0
#define JAL_CLK_DELTA_SHFT                   5
                                             
#define JAL_N_COUNT_ADDR                     (0x000000D0  + JAL_BASE_ADDR)
#define JAL_N_COUNT_MASK                     0x00001F00
#define JAL_N_COUNT_SHFT                     8
                                             
#define JAL_SEL_ADDR                         (0x000000D0  + JAL_BASE_ADDR)
#define JAL_SEL_MASK                         0x00006000
#define JAL_SEL_SHFT                         13
                                             
#define JAL_SUP_BT_CLK_ADDR                  (0x000000D0 + JAL_BASE_ADDR)
#define JAL_SUP_BT_CLK_MASK                  0xFFFF8000
#define JAL_SUP_BT_CLK_SHFT                  15
                                             
#define JAL_HOP_ADDR                         (0x000000D4 + JAL_BASE_ADDR)
#define JAL_HOP_MASK                         0x0000007F
#define JAL_HOP_SHFT                         0

#define JAL_TAP_TP_SEL_ADDR                  (0x000000E0 + JAL_BASE_ADDR)
#define JAL_TAP_TP_SEL_MASK                  0x0000003F
#define JAL_TAP_TP_SEL_SHFT                  0
/*******************************************************************
 *
 *   Define the bit positions for the BT Clock Controls(P6 only)
 *   (the clock gating signals are redundant)
 *******************************************************************/
#define JAL_ADD_BT_CLK_RELATIVE_ADDR         (0x000000F0 + JAL_BASE_ADDR)
#define JAL_ADD_BT_CLK_RELATIVE_MASK         0000000001
#define JAL_ADD_BT_CLK_RELATIVE_SHFT         0

#define JAL_WRITE_ABSOLUTE_BT_CLK_ADDR       (0x000000F0 + JAL_BASE_ADDR)
#define JAL_WRITE_ABSOLUTE_BT_CLK_MASK       0x00000002
#define JAL_WRITE_ABSOLUTE_BT_CLK_SHFT       1
                                             
#define JAL_DELAYED_BT_CLK_UPDATE_ADDR       (0x000000F0 + JAL_BASE_ADDR)
#define JAL_DELAYED_BT_CLK_UPDATE_MASK       0x00000004
#define JAL_DELAYED_BT_CLK_UPDATE_SHFT       2

#define JAL_FREEZE_BT_CLK_ADDR               (0x000000F0 + JAL_BASE_ADDR)
#define JAL_FREEZE_BT_CLK_MASK               0x00000008
#define JAL_FREEZE_BT_CLK_SHFT               3

#define JAL_BT_TEST_CONFIGURE_ADDR           (0x000000F4  + JAL_BASE_ADDR)
#define JAL_BT_TEST_CONFIGURE_MASK           0xFFFFFFFB
#define JAL_BT_TEST_CONFIGURE_SHFT           0

#define JAL_R_MSG_SCO_ADDR                   (0x000000F4  + JAL_BASE_ADDR)
#define JAL_R_MSG_SCO_MASK                   0x00000001
#define JAL_R_MSG_SCO_SHFT                   0

#define JAL_R_MSG_BURST_ADDR                 (0x000000F4  + JAL_BASE_ADDR)
#define JAL_R_MSG_BURST_MASK                 0x00000002
#define JAL_R_MSG_BURST_SHFT                 1

#define JAL_R_MSG_EDR_3_ADDR                 (0x000000F4  + JAL_BASE_ADDR)
#define JAL_R_MSG_EDR_3_MASK                 0x00000004
#define JAL_R_MSG_EDR_3_SHFT                 2

#define JAL_TEST_MSG_TYPE_ADDR               (0x000000F4  + JAL_BASE_ADDR)
#define JAL_TEST_MSG_TYPE_MASK               0x00000078
#define JAL_TEST_MSG_TYPE_SHFT               3

#define JAL_PRBS_INIT_ADDR                   (0x000000F4  + JAL_BASE_ADDR)
#define JAL_PRBS_INIT_MASK                   0x0000FF80
#define JAL_PRBS_INIT_SHFT                   7

#define JAL_R_MSG_DATA_ADDR                  (0x000000F4  + JAL_BASE_ADDR)
#define JAL_R_MSG_DATA_MASK                  0xFFFF0000
#define JAL_R_MSG_DATA_SHFT                  16
/*******************************************************************
 *
 *   Define the bit positions for the LC Revision Code Register
 *
 *******************************************************************/
#define JAL_MINOR_REVISION_ADDR              (0x000000F8 + JAL_BASE_ADDR)
#define JAL_MINOR_REVISION_MASK              0x000000FF
#define JAL_MINOR_REVISION_SHFT              0
                                             
#define JAL_MAJOR_REVISION_ADDR              (0x000000F8 + JAL_BASE_ADDR)
#define JAL_MAJOR_REVISION_MASK              0x0000FF00
#define JAL_MAJOR_REVISION_SHFT              8

/*******************************************************************
*
*      Define the bit positions for the reset controls
*
********************************************************************/
#define JAL_RST_CODE_ADDR                    (0x000000FC + JAL_BASE_ADDR)
#define JAL_RST_CODE_MASK                    0xFF000000
#define JAL_RST_CODE_SHFT                    24
                                             
/****************************************************************
*
*  Define the Transmit and Receive Registers
*
****************************************************************/
#define JAL_TX_ACL_BUF_OFFSET                0x0000200
#define JAL_RX_ACL_BUF_OFFSET                0x0000600 

#if (PRH_BS_CFG_SYS_LMP_EDR_ACL_3_MBPS_MODE_SUPPORTED==1)
#define  JAL_ACL_BUF_LEN                     1022   
#elif (PRH_BS_CFG_SYS_LMP_EDR_ACL_2_MBPS_MODE_SUPPORTED==1)
#define  JAL_ACL_BUF_LEN                     680     
#else                                        
#define  JAL_ACL_BUF_LEN                     340
#endif



/****************************************************************
 *  Define additional constants for hardware
 ****************************************************************/
#define  JAL_MAX_POSITION_ERROR              10

#if (PRH_BS_CFG_SYS_LMP_EDR_ACL_3_MBPS_MODE_SUPPORTED==1)
#define  JAL_MAX_PACKET_LENGTH               1023   
#elif (PRH_BS_CFG_SYS_LMP_EDR_ACL_2_MBPS_MODE_SUPPORTED==1)
#define  JAL_MAX_PACKET_LENGTH               681     
#else 
#define  JAL_MAX_PACKET_LENGTH               341
#endif

#define  JAL_HW_REGISTER_LENGTH     (RX_ACL_BUF_ADDR+ACL_BUF_LEN)

/****************************************************************
*
*  Define the addresses of the main registers and associated
*  fields to allow local caching of registers and checking of
*  field assignments to take place
*  To use a local copy of a register
*  1. Give it a unique meaningful name REGISTER_XXX.
*  2. #define REGISTER_XXX_FIELD FIELD for each FIELD that will be
*     used with this register
*  3
*
****************************************************************/
/*
 * BD_ADDR Register        Low/High Address 00H/04H
 */
#define JAL_COM_CTRL_BD_ADDR_LO_REG_ADDR                   (JAL_BASE_ADDR+0x00)
#define JAL_COM_CTRL_BD_ADDR_HI_REG_ADDR                   (JAL_BASE_ADDR+0x04)

/*
 * Clock Registers         BT_CLK[_OFFSET]  18H/ NATIVE_CLK 1CH
 */
#define JAL_COM_CTRL_BT_CLK_READ_REG_ADDR                  (JAL_BASE_ADDR+0x18)
#define JAL_COM_CTRL_BT_CLK_OFFSET_WRITE_REG_ADDR          (JAL_BASE_ADDR+0x18)
#define JAL_COM_CTRL_NATIVE_CLK_REG_ADDR                   (JAL_BASE_ADDR+0x1C)

/*
 * Common Control Syncword Low/High Address 08H/12H
 */
#define JAL_COM_CTRL_SYNC_LO_REG_ADDR                      (JAL_BASE_ADDR+0x08)
#define JAL_COM_CTRL_SYNC_HI_REG_ADDR                      (JAL_BASE_ADDR+0x0C)

/*
 * Common Control General Purpose Register 1  Address 20H
 */
#define JAL_COM_CTRL_GP1_REG_ADDR                          (JAL_BASE_ADDR+0x20)
                                                           
#define JAL_COM_CTRL_GP1_REG_JAL_PAGE_MASK                 JAL_PAGE_MASK
#define JAL_COM_CTRL_GP1_REG_JAL_SLAVE_MASK                JAL_SLAVE_MASK
#define JAL_COM_CTRL_GP1_REG_JAL_USE_LF_MASK               JAL_USE_LF_MASK
                                                           
#define JAL_COM_CTRL_GP1_REG_JAL_ENCRYPT_MASK              JAL_ENCRYPT_MASK
#define JAL_COM_CTRL_GP1_REG_JAL_AM_ADDR_MASK              JAL_AM_ADDR_MASK
#define JAL_COM_CTRL_GP1_REG_JAL_CRC_INIT_MASK             JAL_CRC_INIT_MASK

/*
 * Common Control General Purpose Register 2  Address 24H
 */
#define JAL_COM_CTRL_GP2_REG_ADDR                          (JAL_BASE_ADDR+0x24)

/*
 * All whitening registers grouped in one u_int32 control word
 */
#define JAL_COM_CTRL_GP2_REG_JAL_WHITEN_MASK               JAL_WHITEN_MASK
#define JAL_COM_CTRL_GP2_REG_JAL_DWH_INIT_MASK             JAL_DWH_INIT_MASK
#define JAL_COM_CTRL_GP2_REG_JAL_DWH2_INIT_MASK            JAL_DWH2_INIT_MASK
#define JAL_COM_CTRL_GP2_REG_JAL_DWH_BY_BT_CLK_MASK        JAL_DWH_BY_BT_CLK_MASK
#define JAL_COM_CTRL_GP2_REG_JAL_DWH_ALL_REG_MASK          JAL_DWH_ALL_REG_MASK
/*
 * Common Control Interrupt Register          Address 28H
 */
#define JAL_COM_CTRL_IRQ_REG_ADDR                          (JAL_BASE_ADDR+0x28)

#define JAL_COM_CTRL_IRQ_REG_JAL_PCM_SYNC_INTR_MSK_MASK     JAL_PCM_SYNC_INTR_MSK_MASK 
#define JAL_COM_CTRL_IRQ_REG_JAL_PKD_RX_HDR_INTR_MSK_MASK   JAL_PKD_RX_HDR_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_PKD_INTR_MSK_MASK          JAL_PKD_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_PKA_INTR_MSK_MASK          JAL_PKA_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM_INTR_MSK_MASK          JAL_TIM_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM0_INTR_MSK_MASK         JAL_TIM0_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM1_INTR_MSK_MASK         JAL_TIM1_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM2_INTR_MSK_MASK         JAL_TIM2_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM3_INTR_MSK_MASK         JAL_TIM3_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_NO_PKT_RCVD_INTR_MSK_MASK  JAL_NO_PKT_RCVD_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_SYNC_DET_INTR_MSK_MASK     JAL_SYNC_DET_INTR_MSK_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_AUX_TIM_INTR_MSK_MASK      JAL_AUX_TIM_INTR_MSK_MASK

#define JAL_COM_CTRL_IRQ_REG_JAL_PCM_SYNC_INTR_CLR_MASK     JAL_PCM_SYNC_INTR_CLR_MASK 
#define JAL_COM_CTRL_IRQ_REG_JAL_PKD_RX_HDR_INTR_CLR_MASK   JAL_PKD_RX_HDR_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_PKD_INTR_CLR_MASK          JAL_PKD_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_PKA_INTR_CLR_MASK          JAL_PKA_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM0_INTR_CLR_MASK         JAL_TIM0_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM1_INTR_CLR_MASK         JAL_TIM1_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM2_INTR_CLR_MASK         JAL_TIM2_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_TIM3_INTR_CLR_MASK         JAL_TIM3_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_NO_PKT_RCVD_INTR_CLR_MASK  JAL_NO_PKT_RCVD_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_SYNC_DET_INTR_CLR_MASK     JAL_SYNC_DET_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_AUX_TIM_INTR_CLR_MASK      JAL_AUX_TIM_INTR_CLR_MASK
#define JAL_COM_CTRL_IRQ_REG_JAL_SER0_WRITE_CLR_MASK        JAL_SER0_WRITE_CLR_MASK

/*
 * Common Control Interrupt Register          Address 2CH
 */
#define JAL_COM_STAT_IRQ_REG_ADDR                           (JAL_BASE_ADDR+0x2C)

#define JAL_COM_STAT_IRQ_REG_JAL_PCM_SYNC_INTR_MASK         JAL_PCM_SYNC_INTR_MASK  
#define JAL_COM_STAT_IRQ_REG_JAL_PKD_RX_HDR_INTR_MASK       JAL_PKD_RX_HDR_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_PKD_INTR_MASK              JAL_PKD_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_PKA_INTR_MASK              JAL_PKA_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_TIM0_INTR_MASK             JAL_TIM0_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_TIM1_INTR_MASK             JAL_TIM1_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_TIM2_INTR_MASK             JAL_TIM2_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_TIM3_INTR_MASK             JAL_TIM3_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_NO_PKT_RCVD_INTR_MASK      JAL_NO_PKT_RCVD_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_SYNC_DET_INTR_MASK         JAL_SYNC_DET_INTR_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_SLEEP_STATUS_MASK          JAL_SLEEP_STATUS_MASK
#define JAL_COM_STAT_IRQ_REG_JAL_AUX_TIM_INTR_MASK          JAL_AUX_TIM_INTR_MASK


/*
 * Transmit Control Register                  Address 30H
 */
#define JAL_TX_CTRL_REG_ADDR                                (JAL_BASE_ADDR+0x30)

#define JAL_TX_CTRL_REG_JAL_TX_LEN_MASK                     JAL_TX_LEN_MASK
#define JAL_TX_CTRL_REG_JAL_TX_TYPE_MASK                    JAL_TX_TYPE_MASK
                                                            
#define JAL_TX_CTRL_REG_JAL_TX_FLOW_MASK                    JAL_TX_FLOW_MASK
#define JAL_TX_CTRL_REG_JAL_TX_ARQN_MASK                    JAL_TX_ARQN_MASK
#define JAL_TX_CTRL_REG_JAL_TX_SEQN_MASK                    JAL_TX_SEQN_MASK
#define JAL_TX_CTRL_REG_JAL_TX_MODE_MASK                    JAL_TX_MODE_MASK
#define JAL_TX_CTRL_REG_JAL_TX_L_CH_MASK                    JAL_TX_L_CH_MASK
#define JAL_TX_CTRL_REG_JAL_TX_P_FLOW_MASK                  JAL_TX_P_FLOW_MASK

/*
 * eSCO Control Register                    Address 34H
 */

#define JAL_ESCO_CTRL_REG_ADDR                              (JAL_BASE_ADDR+0x34)

#define JAL_ESCO_CTRL_REG_JAL_ESCO_TX_LEN_MASK              JAL_ESCO_TX_LEN_MASK
#define JAL_ESCO_CTRL_REG_JAL_ESCO_RX_LEN_MASK              JAL_ESCO_RX_LEN_MASK
#define JAL_ESCO_CTRL_REG_JAL_ESCO_LT_ADDR_MASK             JAL_ESCO_LT_ADDR_MASK
#define JAL_ESCO_CTRL_REG_JAL_SCO_ROUTE_MASK                JAL_SCO_ROUTE_MASK
#define JAL_ESCO_CTRL_REG_JAL_PCM_SLOT_NUM_MASK             JAL_PCM_SLOT_NUM_MASK
#define JAL_ESCO_CTRL_REG_JAL_SFE_EN_MASK                    JAL_SFE_EN_MASK
#define JAL_ESCO_CTRL_REG_JAL_ESCO_PCM_MASK                 JAL_ESCO_PCM_MASK
#define JAL_ESCO_CTRL_REG_JAL_EDR_MODE_MASK                 JAL_EDR_MODE_MASK  
/*
 * Transmit Status Register                   Address 40H
 */
#define JAL_TX_STATUS_REG_ADDR                              (JAL_BASE_ADDR+0x40)

/*
 * PCM Configure Register                   Address 44H
 */
#define JAL_PCM_CFG_REG_ADDR                                (JAL_BASE_ADDR+0x44)

#define JAL_PCM_CFG_REG_JAL_SCO_CFG_MASK                    JAL_SCO_CFG_MASK
#define JAL_PCM_CFG_REG_JAL_SCO_CFG0_MASK                   JAL_SCO_CFG0_MASK
#define JAL_PCM_CFG_REG_JAL_SCO_CFG1_MASK                   JAL_SCO_CFG1_MASK
#define JAL_PCM_CFG_REG_JAL_SCO_CFG2_MASK                   JAL_SCO_CFG2_MASK
#define JAL_PCM_CFG_REG_JAL_SCO_FIFO_MASK                   JAL_SCO_FIFO_MASK

#define JAL_PCM_CFG_REG_JAL_VCI_CLK_SEL_MASK                JAL_VCI_CLK_SEL_MASK
#define JAL_PCM_CFG_REG_JAL_VCI_CLK_SEL_MAP_MASK            JAL_VCI_CLK_SEL_MAP_MASK
#define JAL_PCM_CFG_REG_JAL_CODEC_TYPE_MASK                 JAL_CODEC_TYPE_MASK
#define JAL_PCM_CFG_REG_JAL_VCI_SYNC_DIR_MASK               JAL_VCI_SYNC_DIR_MASK
#define JAL_PCM_CFG_REG_JAL_SYNC_LS_MASK                    JAL_SYNC_LS_MASK
#define JAL_PCM_CFG_REG_JAL_MSB_OUTPUT_MASK                 JAL_MSB_OUTPUT_MASK
#define JAL_PCM_CFG_REG_JAL_1S_INPUT_MASK                   JAL_1S_INPUT_MASK
#define JAL_PCM_CFG_REG_JAL_2S_INPUT_MASK                   JAL_2S_INPUT_MASK
#define JAL_PCM_CFG_REG_JAL_SIGN_EXTENSION_MASK             JAL_SIGN_EXTENSION_MASK

/*
 * Receive Control Register                   Address 48H
 */
#define JAL_RX_CTRL_REG_ADDR                                (JAL_BASE_ADDR+0x48)
                                                            
#define JAL_RX_CTRL_REG_JAL_RX_MODE_MASK                    JAL_RX_MODE_MASK
#define JAL_RX_CTRL_REG_JAL_SYNC_ERR_MASK                   JAL_SYNC_ERR_MASK
#define JAL_RX_CTRL_REG_JAL_ABORT_ON_WRONG_AM_ADDR_MASK     JAL_ABORT_ON_WRONG_AM_ADDR_MASK
#define JAL_RX_CTRL_REG_JAL_ERR_SEL_MASK                    JAL_ERR_SEL_MASK
#define JAL_RX_CTRL_REG_JAL_WIN_EXT_MASK                    JAL_WIN_EXT_MASK

/*
 * Receive Status General Purpose Register    Address 50H
 */
#define JAL_RX_STATUS_GP_REG_ADDR                           (JAL_BASE_ADDR+0x50)
                                                            
#define JAL_RX_STATUS_GP_REG_JAL_RX_LEN_MASK                JAL_RX_LEN_MASK
#define JAL_RX_STATUS_GP_REG_JAL_RX_TYPE_MASK               JAL_RX_TYPE_MASK
                                                            
#define JAL_RX_STATUS_GP_REG_JAL_RX_FLOW_MASK               JAL_RX_FLOW_MASK
#define JAL_RX_STATUS_GP_REG_JAL_RX_ARQN_MASK               JAL_RX_ARQN_MASK
#define JAL_RX_STATUS_GP_REG_JAL_RX_SEQN_MASK               JAL_RX_SEQN_MASK
                                                            
#define JAL_RX_STATUS_GP_REG_JAL_RX_AM_ADDR_MASK            JAL_RX_AM_ADDR_MASK
                                                            
#define JAL_RX_STATUS_GP_REG_JAL_RX_L_CH_MASK               JAL_RX_L_CH_MASK
#define JAL_RX_STATUS_GP_REG_JAL_RX_P_FLOW_MASK             JAL_RX_P_FLOW_MASK
                                                            
#define JAL_RX_STATUS_GP_REG_JAL_RX_PKT_MASK                JAL_RX_PKT_MASK
#define JAL_RX_STATUS_GP_REG_JAL_HEC_ERR_MASK               JAL_HEC_ERR_MASK
#define JAL_RX_STATUS_GP_REG_JAL_CRC_ERR_MASK               JAL_CRC_ERR_MASK

#define JAL_RX_STATUS_GP_REG_JAL_AM_ADDR_ABORT_MASK         JAL_AM_ADDR_ABORT_MASK


/*
 * Receive Status SCO Register                Address 54H
 */
#define JAL_RX_STATUS_SCO_REG_ADDR                          (JAL_BASE_ADDR+0x54)

#define JAL_ESCO_RETRANS_TX_ADDR              (0x00000084 + JAL_BASE_ADDR)
#define JAL_ESCO_RETRANS_TX_MASK              0x00000001
#define JAL_ESCO_RETRANS_TX_SHFT              0
                                             
#define JAL_ESCO_RETRANS_RX_ADDR              (0x000000F8 + JAL_BASE_ADDR)
#define JAL_ESCO_RETRANS_RX_MASK              0x00000002
#define JAL_ESCO_RETRANS_RX_SHFT              1

#define JAL_ESCO_RETRANS_RX_STOP_ADDR              (0x000000F8 + JAL_BASE_ADDR)
#define JAL_ESCO_RETRANS_RX_STOP_MASK              0x00000004
#define JAL_ESCO_RETRANS_RX_STOP_SHFT              2



#define JAL_ESCO_RETRANS_REG_ADDR                          (JAL_BASE_ADDR+0x84)
#define JAL_ESCO_RETRANS_REG_JAL_ESCO_RETRANS_TX_MASK  JAL_ESCO_RETRANS_TX_MASK
#define JAL_ESCO_RETRANS_REG_JAL_ESCO_RETRANS_RX_MASK  JAL_ESCO_RETRANS_RX_MASK
#define JAL_ESCO_RETRANS_REG_JAL_ESCO_RETRANS_RX_STOP_MASK  JAL_ESCO_RETRANS_RX_STOP_MASK



//#define JAL_ESCO_RETRANSMITTE_CODEC_REG_ADDR     (JAL_BASE_ADDR+0x84)


/*
 * Encryption Key Length Register             Address B8H
 */
#define JAL_ENC_KEY_LENGTH_REG_ADDR                         (JAL_BASE_ADDR+0xB8)


/*
 * Serial Interface Adapter Register          Address 60H
 */
#define JAL_SER_CFG_REG_ADDR                                (JAL_BASE_ADDR+0x60)
                                                            
#define JAL_SER_CFG_REG_JAL_SER_CFG_MASK                    JAL_SER_CFG_MASK
#define JAL_SER_CFG_REG_JAL_SER_BUSY_MASK                   JAL_SER_BUSY_MASK
                                                            
                                                            
#define JAL_SER_CTRL_REG_ADDR                               (JAL_BASE_ADDR+0x64)
                                                            
#define JAL_SER_CTRL_REG_JAL_SER_TIME_MASK                  JAL_SER_TIME_MASK
#define JAL_SER_CTRL_REG_JAL_SER_COMBINE_MASK               JAL_SER_COMBINE_MASK
#define JAL_SER_CTRL_REG_JAL_SER_MASK_MASK                  JAL_SER_MASK_MASK
#define JAL_SER_CTRL_REG_JAL_SER_NOW_MASK                   JAL_SER_NOW_MASK
#define JAL_SER_CTRL_REG_JAL_SER_SEQ_MASK                   JAL_SER_SEQ_MASK

#define JAL_SER_DATA0_REG_ADDR                              (JAL_BASE_ADDR+0x70)
#define JAL_SER_DATA1_REG_ADDR                              (JAL_BASE_ADDR+0x74)
#define JAL_SER_DATA2_REG_ADDR                              (JAL_BASE_ADDR+0x78)
#define JAL_SER_DATA3_REG_ADDR                              (JAL_BASE_ADDR+0x7C)


/*
 * Definitions for the Enhanced SER block
 */
#define JAL_SER_ESER_CTRL_REG_ADDR                          (JAL_BASE_ADDR+0x64)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_COMBINE_MASK          (0x00070000)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_MASK_MASK             (0x0000FFFF)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_NOW_MASK              (0x00100000)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_SEQ_MASK              (0x00200000)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_DOUBLE_MASK           (0x00400000)
#define JAL_SER_ESER_CTRL_REG_JAL_SER_MAP_SEL_MASK          (0x00800000)

#define JAL_SER_ESER_CTRL_REG_JAL_SER_COMBINE_BIT_OFFSET    16
#define JAL_SER_ESER_CTRL_REG_JAL_SER_MASK_BIT_OFFSET        0
#define JAL_SER_ESER_CTRL_REG_JAL_SER_NOW_BIT_OFFSET        20
#define JAL_SER_ESER_CTRL_REG_JAL_SER_SEQ_BIT_OFFSET        21
#define JAL_SER_ESER_CTRL_REG_JAL_SER_DOUBLE_BIT_OFFSET     22
#define JAL_SER_ESER_CTRL_REG_JAL_SER_MAP_SEL_BIT_OFFSET    23
#define JAL_SER_ESER_CTRL_REG_JAL_SER_MAP_BUSY_BIT_OFFSET   31



#define JAL_SER_ESER_TIME_REG_ADDR                          (JAL_BASE_ADDR+0x68)
#define JAL_SER_ESER_TIME_0_MASK                            (0x000F)
#define JAL_SER_ESER_TIME_1_MASK                            (0x00F0)
#define JAL_SER_ESER_TIME_2_MASK                            (0x0F00)
#define JAL_SER_ESER_TIME_3_MASK                            (0xF000)
                                                            
#define JAL_SER_ESER_TIME_0_BIT_OFFSET                      0
#define JAL_SER_ESER_TIME_1_BIT_OFFSET                      4
#define JAL_SER_ESER_TIME_2_BIT_OFFSET                      8
#define JAL_SER_ESER_TIME_3_BIT_OFFSET                      12



#define JAL_SER_ESER_DATA_ADDR                              (JAL_BASE_ADDR+0x100) 
#define JAL_SER_ESER_DATA_0_ADDR                            (JAL_SER_ESER_DATA_ADDR)
#define JAL_SER_ESER_DATA_1_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*1)
#define JAL_SER_ESER_DATA_2_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*2)
#define JAL_SER_ESER_DATA_3_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*3)
#define JAL_SER_ESER_DATA_4_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*4)
#define JAL_SER_ESER_DATA_5_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*5)
#define JAL_SER_ESER_DATA_6_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*6)
#define JAL_SER_ESER_DATA_7_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*7)
#define JAL_SER_ESER_DATA_8_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*8)
#define JAL_SER_ESER_DATA_9_ADDR                            (JAL_SER_ESER_DATA_ADDR+4*9)
#define JAL_SER_ESER_DATA_10_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*10)
#define JAL_SER_ESER_DATA_11_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*11)
#define JAL_SER_ESER_DATA_12_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*12)
#define JAL_SER_ESER_DATA_13_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*13)
#define JAL_SER_ESER_DATA_14_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*14)
#define JAL_SER_ESER_DATA_15_ADDR                           (JAL_SER_ESER_DATA_ADDR+4*15)


/*
 * Piconet ctrl Register                      Address A4H
 */
#define JAL_PICONET_CTRL_REG_ADDR                           (JAL_BASE_ADDR+0xA4)

#define JAL_PICONET_CTRL_REG_JAL_PICONET_INDEX_MASK         JAL_PICONET_INDEX_MASK
#define JAL_PICONET_CTRL_REG_JAL_SWITCH_PICONET_CLK_MASK    JAL_SWITCH_PICONET_CLK_MASK
#define JAL_PICONET_CTRL_REG_JAL_UPDATE_PICONET_CLK_MASK    JAL_UPDATE_PICONET_CLK_MASK

/*
 * Hop Selection Control Register             Address D0H (temp 9CH)
 *                                            see register definitions
 */
#define JAL_HSE_CONTROL_REG_ADDR                            (JAL_BASE_ADDR+0xD0)
                                                            
#define JAL_HSE_CONTROL_REG_JAL_SYS_MASK                    JAL_SYS_MASK
#define JAL_HSE_CONTROL_REG_JAL_H_PAGE_MASK                 JAL_H_PAGE_MASK
#define JAL_HSE_CONTROL_REG_JAL_H_SLAVE_MASK                JAL_H_SLAVE_MASK
#define JAL_HSE_CONTROL_REG_JAL_PAGE_OFFSET_MASK            JAL_PAGE_OFFSET_MASK
#define JAL_HSE_CONTROL_REG_JAL_INDEX_MAP_MASK              JAL_INDEX_MAP_MASK
#define JAL_HSE_CONTROL_REG_JAL_CLK_DELTA_MASK              JAL_CLK_DELTA_MASK
#define JAL_HSE_CONTROL_REG_JAL_N_COUNT_MASK                JAL_N_COUNT_MASK
#define JAL_HSE_CONTROL_REG_JAL_SEL_MASK                    JAL_SEL_MASK
#define JAL_HSE_CONTROL_REG_JAL_SUP_BT_CLK_MASK             JAL_SUP_BT_CLK_MASK

/*
 * Hop Selection Control Register             Address D4H
 */
#define JAL_HSE_HOP_REG_ADDR                                (JAL_BASE_ADDR+0xD4)
#define JAL_HSE_HOP_REG_JAL_HOP_MASK                        JAL_HOP_MASK

/*
 * Hop Selection Registers V1.2               Address D0-DC
 * No fields, since there is only a single one in each register.
 *  Addr       b7     b6     b5     b4     b3     b2     b1     b0
 *  CONTROL +------+------+------+------+------+------+------+------+
 *  D0      |    HSE_BT_CLK[27:0]                                   |
 *          +------+------+------+------+------+------+------+------+
 *  D4      |    HSE_UAP_LAP[23:0]                                  |
 *          +------+------+------+------+------+------+------+------+
 *  D8      |    HSE_SUM[23:0]                                      |
 *          +------+------+------+------+------+------+------+------+
 *  DC      |    HSE_RF_CHAN_INDEX[6:0]                             |
 *          +------+------+------+------+------+------+------+------+
 */
#define JAL_HSE_BT_CLK_REG_ADDR                             (JAL_BASE_ADDR+0xD0)
#define JAL_HSE_UAP_LAP_REG_ADDR                            (JAL_BASE_ADDR+0xD4)
#define JAL_HSE_SUM_REG_ADDR                                (JAL_BASE_ADDR+0xD8)
#define JAL_HSE_RF_CHAN_INDEX_REG_ADDR                      (JAL_BASE_ADDR+0xDC)

#if (PRH_BS_CFG_SYS_SCO_REPEATER_SUPPORTED==1)
/*******************************************************************
 *
 *   Define the bit positions for the SCO Repeater Controls(Tama only)
 *   (NT clock phase offset is also adjustable when hit by RX packet)
 *******************************************************************/
#define JAL_SCO_REPEATER_BIT_ADDR                           (0x000000F0 + JAL_BASE_ADDR)
#define JAL_SCO_REPEATER_BIT_MASK                           0x000000010
#define JAL_SCO_REPEATER_BIT_SHFT                           4
#endif

#endif

